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| preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. march 2006 rev 4 1/77 1 stw4810 power management for multimedia processors feature summary 2 step-down converters ? 1 to 1.5v with 15 steps at 600ma ? 1.8v at 600ma for general purpose usage 3 low-drop output regulators for different uses ? pll analog supplies: 1.05v, 1.2v, 1.3v 1.8v - 10ma ? processor analogue functions: 2.5v - 10ma ? auxiliary device: 1.5v, 1.8v, 2.5v, 2.8v - 150 ma usb otg module ? full and low speed usb otg transceiver ? charge-pump (5v, 100ma) for usb cable mass memory cards (sd/mmc/sdio) ? 1 linear regulator: 1.8v, 2.85v, 3v - 150ma ? level shifter miscellaneous ? 32 khz control for multimedia processor ? processor supply monitoring ? processor reset control ? 2 serial i2c interfaces description stw4810 is a power management companion chip for multimedia processors used in portable applications. it supplies the multimedia processor including its memories and peripherals. stw4810 supports the main mass memory standard cards. sdio tm is also supported and allows to connect multimedia peripherals like cameras. application st nomadik tm stn88xx multimedia processor mobile phones, pda, videophonerev 4 order codes 6x6x1.2mm 0.5mm pitch tfbga 84 4.6x4.6x1.0mm 0.4mm pitch vfbga 84 stw4810bhd stw4810bra part number package packing stw4810bhd/lf tfbga84- 6x 6 x 1.2 mm / 0.5 mm pitch tray stw4810bra/lf vfbga 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch tray www.st.com
contents stw4810 2/77 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.1 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.2 power off / vddok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 it generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.7 clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 vcore regulator: dc/dc step- down regulator . . . . . . . . . . . . . . . 35 4.3.3 vio_vmem regulator: dc/dc step- down regulator . . . . . . . . . . . . . . . 35 4.3.4 vpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.5 vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.6 vaux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.7 power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.8 power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.9 thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4 usb otg module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4.2 modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.3 usb enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 sd/mmc/sdio module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 stw4810 contents 3/77 5 electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 vref18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.3 vcore dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.4 vio_vmem dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.5 ldo regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.6 power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4 digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4.1 cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . 57 5.4.2 cmos input/output dynamic characteristics: i2c interface . . . . . . . . . . 58 5.4.3 cmos input/output static characteristics: vio level . . . . . . . . . . . . . . . 59 5.4.4 cmos input/output static characteristics: v bat level . . . . . . . . . . . . . . . 61 5.4.5 cmos input/output static characteristics: vmmc level . . . . . . . . . . . . . 62 5.5 usb otg transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6 sd/mmc card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1 components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.1 tfbga 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.2 vfbga 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 list of tables stw4810 4/77 list of tables table 1. stw4810 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. stw4810 balls function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. usb register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. vendor id and product id: read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. usb control register 1 (address = 04h set and 05h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. usb control register 2 (address = 06h set and 07h clearh) . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. usb interrupt source register (address = 08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. usb interrupt latch registers (address = 0ah set and 0bh clearh) . . . . . . . . . . . . . . . . . . . 25 table 15. usb interrupt mask false register (address = 0ch and 0dh) . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. usb interrupt mask true register (address = 0eh and 0fh) . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. usb en register (address = 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. sd mmc control register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. power control register - general information (address = 1eh) . . . . . . . . . . . . . . . . . . . . . . 28 table 20. power control register - general information (address = 1fh) . . . . . . . . . . . . . . . . . . . . . . 28 table 21. power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22. power control register at address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23. power control register at address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. power control register at address 07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. power control register at address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 26. power control register at address 09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. power control register at address 0ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. twarning register (address = 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 29. power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 30. thermal threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 31. data transmission via usb control register 1 (dat_se0 mode) - suspend = 0 . . . . . . . . 42 table 32. data transmission via usb control register 1 (dat_se0 mode) - suspend = 1 . . . . . . . . 42 table 33. data receiver via usb control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 34. stw4810 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 35. package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 36. operating conditions (temp range: -30 to +85 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 37. vref18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 38. vcore dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 39. vio_vmem dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 40. ldo regulators - vpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 41. ldo regulators - vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 42. ldo regulators - vaux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 43. power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 44. cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 45. cmos input/output dynamic characteristics: i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 46. vio level: usb and control i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 47. vio level: mmc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 48. cmos input/output static characteristics: vbat level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 stw4810 list of tables 5/77 table 49. cmos input/output static characteristics vmmc level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 50. usb otg transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 51. sd/mmc card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 52. components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 53. recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 55. tfbga 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 72 table 56. vfbga 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 74 table 57. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 list of figures stw4810 6/77 list of figures figure 1. typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. stw4810 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. .switching power to sleep timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. vddok block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. i2c interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. control interface: i2c format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. control interface: i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. clock switching between master and internal clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. thermal threshold temperatures for ?it_warn? bit and vddok ball . . . . . . . . . . . . . . . . . . . 38 figure 12. usb otg transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 figure 13. sd mmc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14. propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 15. stw4810 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 16. tfbga 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 73 figure 17. vfbga 84 balls 4.6x4.6x1.0 mm ball pitch drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 stw4810 overview 7/77 1 overview the stw4810 power management device has the following features; power management module ? 1 step-down converter for processor core (1 to 1.5 v with 15 steps at 600 ma) ? 1 step-down converter (1.8 v at 600 ma) for general purpose usage such as processor input/output supply, external memory, ddr and sdram and peripherals ? 1 low-drop output regulator for analog supplies, such as pll (1.05 v, 1.2 v, 1.3 v, 1.8 v at 10 ma) ? 1 low-drop output regulator for processor analogue functions (2.5 v at 10 ma) ? 1 low-drop output regulator for auxiliary devices (1.5 v, 1.8 v, 2.5 v, 2.8 v at 150 ma) usb otg module ? full and low speed usb otg transceiver ? 1 linear regulators (3.1 v at 40 ma) supplying transceiver ? 1 charge-pump (5 v at 100 ma) supplying vbus line of the usb cable mass memory cards (sd/mmc/sdio) ? 1 linear regulator (1.8 v, 2.85 v, 3 v at 150 ma) ? level shifter miscellaneous ? 32 khz control for multimedia processor ? processor supply monitoring ? processor reset control ? 2 serial i2c interfaces figure 1. typical mobile multimedia system functional block diagram stw4810 8/77 2 functional block diagram figure 2. stw4810 block diagram vpll_ldo 1.05v,1.2v,1.3v,1.8v, vaux vcore vbat_vcore vminus_vcore vpll vana_ldo 2.5v, 10ma vana vbat_vpll_ana vbat_vio_vmem vlx_vio_vmem vminus_vio_vmem vio_vmem 1.8v- 600ma vref_vio_vmem vref_vcore vref_vpll soft_start vaux_ldo 1.5v,1.8v2.5v,2.8v, vref_18 bg buffer bias vref_vaux thermal shutdown vbat_ana internal oscillator clock switching and control master_clk scl sda i2c interface vbat_dig vminus_dig general control pon vddok porn pwren sw_resetn control registers usb control usb otg transceiver interface vbat_usb id cp cn vbus dp dn charge pump vusb 3.1v - 40ma 5v - 100ma driver usboen usbvp usbvm usbrcv control sd/mmc/ sd/ mmc/sdio interface 1.8/2.85/3v-150ma vbat_mmc vmmc driver level shifter latchclk clkout dataout0 cmdout dataout[3:1] mcclk mcfbclk mccmddir mcdat0dir mcdat2dir mccmd mcdata[3:1] mcdata0 request_mc vbat_vaux clk32k clk32k_in porn_vbat vminus_ana 1v=>1.5v- 600ma vlx_vcore tcxo_en monitoring it_wake_up gpo1 gpo2 i2c mux usbscl usbsda usbintn mcdat31dir vminus_usb level shifter pull up & down sdio control 10ma 150ma stw4810 ball information 9/77 3 ball information 3.1 ball connections 3.2 ball functions stw4810 includes the following ball types vddd/vdda: digital/analog power supply vssd/vssa: digital/analog ground supply do/di/dio: digital output / digital input / digital input output doz: digital output with high impedance capability ao/ai/aio: analog output / analog input / analog input-output g: to be connected to ground o: to be left open int-ref: associated to internal reference ta b l e 2 details the ballout. table 1. stw4810 ball connections 12345678910 a clk32k_in vminus_ vio_vmem vlx_vio_ vmem vbat_vio_ vmem vio_vmem vaux vana vpll vref_18 vcore b ?reserved? request_ mc vminus_ vio_vmem vbat_vio_ vmem vminus_ ana vbat_ vaux ?reserved? ?reserved? ?reserved? vminus_ vcore c tcxo_en it_wake_ up vminus_ dig vlx_vio_ vmem ?reserved? vbat_ana vbat_ vpll_ana pon vminus_ vcore vlx_ vcore d vbat_dig master_ clk ?reserved? vlx_ vcore vbat_ vcore vbat_ vcore e dataout0 dataout <1> dataout <2> id dp dn f dataout <3> cmdout latchclk ?reserved? vbat_usb vusb g clkout mcclk mccmd dir ?reserved? usbscl vbus h mccmd mcdata <3> mcdata <1> mcdata31 dir mcfbclk pwren sda usbintn usbsda cp j mcdata <2> vddok porn vbat_ mmc gpo1 scl usbvp usbvm vminus_ usb cn k mcdata0 mcdat0 dir clk32k sw_ reset vmmc gpo2 usbrcv usboen mcdat2 dir ?reserved? ball information stw4810 10/77 table 2. stw4810 balls function ball ball name ball type description general supplies d1 vbat_dig vddd-vbat battery supply for digital/oscillator c3 vminus_dig vssd ground for digital and oscillator c6 vbat_ana vdda-vbat battery supply for analog b5 vminus_ana vssa ground for analog f9 vbat_usb vdda-vbat battery supply for usb block j9 vminus_usb vssa ground for usb block a9 vref_18 int-ref internal reference control balls c8 pon di(vbat) pull down 1.5m ? power-on and reset k4 sw_resetn di(vio_vmem) pull up 1.5m ? software reset, reset all applications when sw_resetn = 0 j2 vddok do(vio_vmem) supply monitoring for multimedia processors. interruption for high temperature warning j3 porn do(vio_vmem) multimedia processor resetn h6 pwren di(vio_vmem) pull up 1.5m ? sleep mode from multimedia processor c1 tcxo_en di(vio_vmem) pull down 1.5m ? request of master clock from modem part b2 request_mc do(vio_vmem) request to master clock oscillator j6 scl di(vio_vmem) clock for main i2c interface h7 sda dio(vio_vmem) sda for main i2c interface d2 master_clk ai pull down 1.5m ? 26 mhz, 13 mhz or 19.2 mhz from modem a1 clk32k_in di(vio_vmem) pull down 1.5m ? 32 khz input k3 clk32k do(vio_vmem) 32 khz to multimedia processor stw4810 ball information 11/77 regulator balls a4 b4 vbat_vio_vmem vdda-vbat battery power supply for step down vio_vmem a2 b3 vminus_vio_vmem vssa ground for step down vio_vmem a3 c4 vlx_vio_vmem aio buck of step down vio_vmem a5 vio_vmem ai vio_vmem feed back input d9 d10 vbat_vcore vdda-vbat battery power supply for step down vcore b10 c9 vminus_vcore vssa ground for step down vcore c10 d8 vlx_vcore aio buck of step-down vcore a10 vcore ai vcore sense c7 vbat_vpll_ana vdda-vbat battery supply for vpll, vana a7 van a ao vana output a8 vpll ao vpll output a6 vaux ao vaux output b6 vbat_vaux vdda-vbat battery supply for vaux usb balls c2 it_wake_up do(vbat-dig) interrupt to modem for wake-up due to usb plug k8 usboen dio(vio_vmem) pull down 1.5m ? output enable of the differential driver in the usb mode j7 usbvp dio(vio_vmem) pull down 1.5m ? data input in the usb transmit mode, positive data input the single-ended transmit mode, or txd in uart mode j8 usbvm dio(vio_vmem) pull down 1.5m ? single-ended zero input in the usb transmit mode, negative data input in the single-ended transmit mode, or rxd in the uart mode k7 usbrcv do(vio_vmem) differential receiver output e9 dp aio(vusb) positive data line in the usb mode, or serial data input in the uart mode e10 dn aio(vusb) negative data line in the usb mode, or serial data output in the uart mode. e8 id ai(vbat-usb) id ball of the usb detector used for protocol identification. table 2. stw4810 balls function (continued) ball ball name ball type description general supplies ball information stw4810 12/77 h10 cp aio(vbus) c plus flying capacitor (vbus level 4.4 to 5.25) j10 cn aio(vbus) c minus flying capacitor (vbus level) g10 vbus aio(vbus) usb cable supply (vbus level) f10 vusb aio decoupling capacitor for usb internal regulator g9 usbscl di(vio_vmem) clock for dedicated usb i2c h9 usbsda dio(vio_vmem) sda for dedicated usb i2c h8 usbintn do(vio_vmem) interrupt to multimedia processor for usb or accessory plug sd mmc balls g3 mccmddir di(vio_vmem) pull down 1.5m ? cmd direction. - ?high?: cmd signal from processor to card - ?low?: cmd signal from card to processor k2 mcdat0dir di(vio_vmem) pull down 1.5m ? data0 direction - ?high?: data0 signal from processor to card - ?low?: data0 signal from card to processor k9 mcdat2dir di(vio_vmem) pull down 1.5m ? data2 direction - ?high?: data2 signal from processor to card - ?low?: data2 signal from card to processor h4 mcdat31dir di(vio_vmem) pull down 1.5m ? data(3,1) direction - ?high?: data(3,1) signal from processor to card - ?low?: data(3,1) signal from card to processor g2 mcclk di(vio_vmem) pull down 1.5m ? host clock, between processor and stw4810, to the card (processor clock). h5 mcfbclk do(vio_vmem) host feedback clock between stw4810 and processor, to re-synchronize data in processor. h1 mccmd dio(vio_vmem) pull up 1.5m ? bidirectional command/response signal between processor and stw4810. k1 mcdata0 dio(vio_vmem) pull up1.5m ? bidirectional data0 between processor and stw4810 h2 h3 j1 mcdata[3:1] dio(vio_vmem) pull up 1.5m ? bidirectional data [3:1] between processor and stw4810. f3 latchclk di(vmmc) pull down 1.5m ? host feedback clock to stw4810, to re- synchronize data in processor. g1 clkout do(vmmc) host clock, between stw4810 and card (processor clock). f2 cmdout dio(vmmc) pull up 1.5m ? bidirectional command/response signal between stw4810 and processor. table 2. stw4810 balls function (continued) ball ball name ball type description general supplies stw4810 ball information 13/77 e1 dataout0 dio(vmmc) pull up 1.5m ? bidirectional data0 between stw4810 and card f1 e3 e2 dataout[3:1] dio(vmmc) pull up 1.5m ? bidirectional data[3:1] between stw4810 and card. j4 vbat_mmc vdda-vbat battery supply for vmmc k5 vmmc aio vmmc supply output other balls j5 gpo1 ao general purpose output k6 gpo2 ao general purpose output b9 d3 ?reserved? g to be connected to ground b1 b7 b8 c5 f8 g8 k10 ?reserved? o to be left open table 2. stw4810 balls function (continued) ball ball name ball type description general supplies functional description stw4810 14/77 4 functional description 4.1 introduction the stw4810 integrates all the power supplies for a multimedia processor as well as memories and peripherals: two switched mode power supply regulators: one for the multimedia processor core, one for multimedia processor i/os and memories three low-drop output regulators for multimedia processor analog supplies (pll and others) and auxiliary components usb otg fs/ls physical interface mmc card power supplies and level shifters multimedia processor supply monitoring / power-on reset and power supply alarms / interrupt management two serial i2c communication interfaces; one to control the devices (sda, scl) and one to control the usb (usbsda, usbscl). 4.2 digital control module this module describes the interfaces used to program the device and the related registers. 4.2.1 state machine description of each states: ( figure 3. ) off: in this mode the stw4810 is switched off. off is when pon=0, when battery level is under 2.4 v or when thermal shutdown is activated. there is no multimedia processor power supply. the only active cell is the usb cable detection and v bat level detection. osc_start: oscillator is enabled and the power up module is waiting for the rising edge of the internal signal osc_ok to start power up sequence. this state duration is 300 s. start_bias: bias, reference and thermal shut-down are enabled, a counter is activated to wait for rising edge of internal signals pdn_regulators. this state duration has a typical value of 7.77 ms and a worst case value of 9.46 ms. start_pm: after a 1 ms wait, multimedia processor power supplies are available (vio_vmem, vcore, vpll, and vana). the device can allow i2c communication, output power supply monitoring and application (usb,sd/mmc). off2: stw4810 is waiting for the 32 khz multimedia processor signal. this state has an indeterminate duration. if 32khz is present during the states describes above, it has no effect. the 32 khz signal is taken into account by stw4810 only when the ?vddok? ball is high, that is at the end of start_pm state. reset: stw4810 forces a reset during 10*32 khz period before setting porn high. int_osc: the stw4810 can work without master_clk via its internal oscillator. the device waits for an external clock detection before switching to the external clock. when receiving a rising edge on pwren ball (coming from multimedia processor) or on tcxo_en ball (coming from modem), stw4810 answers by asserting to ?1? the stw4810 functional description 15/77 request_mc ball. stw4810 remains in internal oscillator mode until it receives the external clock signal on master_clk ball. ext_clk: when master_clk is detected, the stw4810 uses this clock as reference and switches off its internal oscillator to save quiescent. masterclk should remain connected up to sleep mode. sleep: sleep mode is required by multimedia processor by setting a pwren at low level. then vddok is forced to 0, regulators (vcore, vio_vmem) switch to sleep mode and wait for pwren at high level ( figure 4 ). wake-up: from sleep mode, the multimedia processor requests to switch back to normal mode. thus the device restarts its internal oscillator and then switches regulators from sleep to normal mode and informs multimedia processor with vddok at high level ( figure 4 ). note: by default vaux is in stand by mode, pdn_vaux = 0 ( ta b l e 1 8 ). it can be programmed in normal mode only by asserted pdn_vaux bit to ?1?. functional description stw4810 16/77 figure 3. start-up timing all regulators are started with pdn_regulators but can be switched off from the beginning or during application by software ( ta b l e 2 7 ) pon ball pdn__osc pdn_regulators vddok ball clk32k_in ball porn ball pwren ball off start_pm reset 1ms int_osc tcxo_en ball internal_osc 10*(1/32khz) off2 master_clk ball request_mc ball vbat 300s 9.38ms (11ms wc) reset start_bias 7.77ms (9.46ms wc) ?or? delays are worst case maximum delays voutput(s) ball vpll / vio_vmem vcore clk32k ball (*) (*) if 32 khz available before vddok signal rising edge, off2 state duration is null stw4810 functional description 17/77 figure 4. .switching power to sleep timing registers reset in the event of a hardware reset coming from the modem, pon ball set to ?0?, all registers are reset at initial value when pon ball goes back to ?1? level. a software reset from multimedia processor of stw4810, through sw_resetn ball set to ?0?, reset all registers except power control register (at address 1e & 1f). main clock oscillator control request_mc is an or output gate between pwren (coming from multimedia processor) and tcxo_en (coming from modem supply), it is synchronized on 32 khz, except during power-up where pwren is masked and considered as high. request_mc enabled or disabled the master clock oscillator device. pdn_regulators vddok clk32k pwren sleep regulators hpm sleep hpm master_clk internal_osc pdn_intosc int_osc _detect ~100s request_mc functional description stw4810 18/77 4.2.2 power off / vddok in case of vddok falling edge due to under voltage on vcore or vio_vmem detected, or ?it_twarn? bit set to ?1? ( ta b l e 1 8 ), then multimedia processor is reset (porn low during a minimum time of 312.5 s) and restarted with no time-out. (see figure 5 ). in case of vddok falling edge because pwren balls equals ?0?, there is no reset (porn still high). in case of pon falling edge (stw4810 switched off from modem) multimedia processor is also reset with no time-out. we consider that clean switch off between modem and multimedia processor is done by software directly. figure 5. vddok block diagram 4.2.3 sleep mode stw4810 goes into sleep mode by different ways. whether vcore, vio_vmem and vaux are programmed to sleep mode or not is indicated in ta b l e 2 7 . digital block & vcore_monitor vio_monitor & vddok it_twarn reg status register reset after read operation or pon falling edge or porn_vbat. mask_twarn vddok porn 312.5 s (10* 32 khz) under voltage detection operating voltage threshold value reached pwren stw4810 functional description 19/77 4.2.4 i2c interface the device supports two i2c bus interfaces. one main interface (sda,scl) controls power management and all programmable functions, the second interface (usbsda, usbscl) is dedicated to usb control. stw4810 allows to work with only the main i2c interface to control all the functions, including the usb, via usb_i2c_ctrl bit of power control register ( ta b l e 2 7 ). i2c interface is used to read status information from inside the device. flags, interrupt and write registers are used to configure the device functions (threshold, clock division, output voltage, etc....). by default, the main i2c interface (scl,sda) controls the main registers and usb i2c interface (usbscl, usbsda) controls usb registers. figure 6. i2c interface block diagram both i2c are configured as slave serial interface compatible with i2c registered trademark of phillips inc. (version 2.1). i2c interface description stw4810 i2c is a slave serial interface with a serial data line (sda or usbsda) and a serial clock line (scl or usbscl): ? scl / usbscl: input clock used to shift data ? sda / usbsda: input/output bidirectional data transfers it is composed of: ? one filter to reject spikes on the bus data line and preserve data integrity ? bidirectional data transfers up to 400kbit/s (fast-mode) via sda or usbsda signal the sda or usbsda signal contains the input/output control and data signals that are shifted in the device, msb first. the first bit must be high (start) followed by the device id (7 bits) and read/write bit control (1 indicates read access, a logical 0 indicates a write access). ? device id in write mode: 5ah (01011010) ? device id in read mode: 5bh (01011011) then stw4810 sends an acknowledge at the end of an 8 bits transfer. the next 8 bits correspond to the register address followed by another acknowledge. the 8 bits data field is sent last, followed by a last acknowledge. main registers sda usbscl scl mux sda or usbsda scl or usbscl usbsda usb registers sda scl usb_i2c_ctrl functional description stw4810 20/77 i2c interface modes figure 7. control interface: i2c format figure 8. control interface: i2c timing table 3. device id b7 b6 b5 b4 b3 b2 b1 b0 adrid6 adrid5 adrid4 adrid3 adrid2 adrid1 adrid0 r/w table 4. register address b7 b6 b5 b4 b3 b2 b1 b0 regadr7 regadr6 regadr5 regadr4 regadr3 regadr2 regadr1 regadr0 table 5. register data b7 b6 b5 b4 b3 b2 b1 b0 data7 data6 data5 data4 data3 data2 data1 data0 device address 0 1 0 1 1 0 1 0 regn address regn data in write single byte start ack ack ack stop device address 0 1 0 1 1 0 1 0 regn address start ack ack device address 0 1 0 1 1 0 1 1 regn data out start ack no ack random addr single byte read device address 0 1 0 1 1 0 1 0 regn address start ack ack device address 0 1 0 1 1 0 1 1 start reg n data out ack no ack stop m+1 data bytes ack reg n + m data out random addr multi byte read ack stop start repeated stop t buf t hd_sta t f t low t r t high t hd_dat t su_dat start sda scl t su_sta t hd_sta t su_sto usbsda usbscl stw4810 functional description 21/77 4.2.5 control registers control registers have the following functions: ? select level of regulation for multimedia processor supply ? control the usb interface ? control the sd/mmc/sdio interface ? control the state machine table 6. register general information address comment i2c control 00h to 10h usb registers ( ta b l e 9 to ta bl e 1 7 ) usbsda / usbscl or sda / scl (1) 11h sd mmc control register ( ta bl e 1 8 ) sda / scl 12h to 1dh test registers 1eh to 1fh power control registers ( ta b l e 1 9 to ta b l e 2 7 ) sda / scl 20h twarning register ( ta bl e 2 8 ) sda / scl 1. controlled by usb_i2c_ctrl bit of power control register ( ta bl e 2 7 ) table 7. register summary register addr. 7 6 5 4 3 2 1 0 vendor id 00h10000011 01h00000100 product id 02h00010000 03h01000000 usb control register 1 04h 05h not used uart_en oe_int_ en bdis_ acon_en not used dat_se0 suspend speed usb control register 2 06h 07h vbus_ chrg vbus_ dischrg vbus_ drv id_gnd dn_ pulldown dp_ pulldown dn_ pullup dp_ pullup usb interrupt source 08h cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld usb interrupt latch 0ah 0bh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld usb interrupt mask false 0ch 0dh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld usb interrupt mask true 0eh 0fh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld usb en 10h not used usb_en not used sd mmc control 11h pdn_ vaux it_warn monitori ng_vio_ vmem_ vcore gpo2 gpo1 sel_vmmc<1:0> pdn_ vmmc twarning 20h not used mask_ twarn functional description stw4810 22/77 registers controlled by i2c usb bus the registers described in this chapter are controlled through the usb serial i2c interface, usbscl and usbsda balls. these registers could also be controlled through the main i2c interface, scl and sda balls by setting to ?1? usb-i2c_ctrl bit in power control register ( ta b l e 2 3 ). note: a bit of register 1 is set at ?1? by writing a ?1? at address 04h, is reset at ?0? by writing a ?1? at address 05h. this is also applicable for usb control register 2 (06h, 07h), usb interrupt register (0ah,0bh), usb interrupt mask false register (0ch, 0dh) and usb interrupt mask true register (0eh, 0fh). writing ?0? at any address has not effect on the content of any register. table 8. power control register register addr. 15 14 13 12 11 10 9 8 power control 1fh not used reg address 2 bits register addr. 7 6 5 4 3 2 1 0 power control 1 eh reg address 3 bits data din/dout 4 bits ena write table 9. usb register address address register type 00h - 01h vendor id r 02h - 03h product id r 04h set usb control register 1 r/w 05h clearh usb control register 1 r/w 06h set usb control register 2 r/w 07h clearh usb control register 2 r/w 08h usb interrupt source r 09h not used 0ah set usb interrupt latch r/w 0bh clearh usb interrupt latch r/w 0ch set usb interrupt mask false r/w 0dh clearh usb interrupt mask false r/w 0eh set usb interrupt mask true r/w 0fh clearh usb interrupt mask true r/w 10h usb_en r/w stw4810 functional description 23/77 usb control register 1 table 10. vendor id and product id: read only name address register value vendor id 00h 83h vendor id 01h 04h product id 02h 10h 03h 40h table 11. usb control register 1 (address = 04h set and 05h clearh) register 76543210 bit name not used uart_en oe_int_ en bdis_ acon_en not used dat_se0 suspend speed type - r/w r/w r/w - r/w r/w r/w bits name value settings default 6 uart_en 0 1 inactive uart logic buffers are enabled 0 5 oe_int_en 0 1 inactive allow to send interruption through usboen 0 4 bdis_acon_en 0 1 inactive (default) enable a-device to connect if b-device disconnect detected: 0 2 dat_se0 0 1 vp_vm usb mode dat_se0 usb mode 0 1 suspend 0 1 inactive (default) put transceiver in low power mode 0 0 speed 0 1 set rise and fall times of transmit low speed full speed 0 functional description stw4810 24/77 usb control register 2 table 12. usb control register 2 (address = 06h set and 07h clearh) register 76543 210 bit name vbus_ chrg vbus_ dischrg vbus_ drv id_gnd dn_ pulldown dp_ pulldow n dn_ pullup dp_ pullup type r/w r/w r/w r/w r/w r/w r/w r/w bits name value settings default 7 vbus_chrg 0 1 inactive charge vbus through a resistor 0 6 vbus_dischrg 0 1 inactive discharge vbus through a resistor to ground. 0 5 vbus_drv 0 1 inactive provide power to vbus 0 4 id_gnd 0 1 inactive connect id ball to ground 0 3 dn_pulldown 0 1 inactive connect dn pull-down 0 2 dp_pulldown 0 1 inactive connect dp pull-down 0 1 dn_pullup 0 1 inactive connect dn pull-up 0 0 dp_pullup 0 1 inactive connect dp pull-up 0 stw4810 functional description 25/77 usb interrupt source register usb latch register usb interrupt latch register bits indicate which sources have generate an interrupt. table 13. usb interrupt source register (address = 08h) register 76543210 bit name cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vld vbus_ vld type rrrrrrrr bits name value settings default 7cr_int 0 1 inactive dp ball is above the carkit interrupt threshold 0 6 bdis_acon 0 1 inactive set when bdis_acon_en is set, and transceiver asserts dp_pullup after detecting b-device disconnect. 0 5 id_float 0 1 inactive id ball floating 0 4 dn_hi 0 1 inactive dn ball is high 0 3 id_gnd_forced 0 1 inactive id ball grounded 0 2 dp_hi 0 1 inactive dp asserted during srp, 0 1 sess_vld 0 1 session valid comparator threshold <0.8v or >4.4v 0.8v < session valid comparator threshold < 4.4v 0 0 vbus_vld 0 1 a-device vbus valid comparator threshold <4.4v a-device vbus valid comparator threshold >4.4v 0 table 14. usb interrupt latch registers (address = 0ah set and 0bh clearh) register 76543210 bit name cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vld vbus_ vld default 00000000 type r/w r/w r/w r/w r/w r/w r/w r/w functional description stw4810 26/77 usb interrupt mask false register usb interrupt mask false register bits enable transition from true to false. usb interrupt mask true register usb interrupt mask true register bits enable interrupts on transition from false to true. usb en register table 15. usb interrupt mask false register (address = 0ch and 0dh) register 76543210 bit name cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl d vbus_vl d default 00000000 type r/w r/w r/w r/w r/w r/w r/w r/w table 16. usb interrupt mask true register (address = 0eh and 0fh) register 76543210 bit name cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl d vbus_vl d type r/w r/w r/w r/w r/w r/w r/w r/w table 17. usb en register (address = 10h) register 76543210 bit name not used usb_en not used type ------r/w- bits name value settings default 1 usb_en 0 1 inactive enable usb phy 0 stw4810 functional description 27/77 registers controlled by main i2c bus i2c controlled registers are controlled through the main serial i2c interface, scl and sda balls. sd mmc control register in flash otp two registers allow to program stw4810 energy management part. these two registers are at address 1e and 1f and must be programmed with 1f register first followed by 1e register. table 18. sd mmc control register (11h) register 76543210 bit name pdn_ vaux it_warn monitori ng_vio_ vmem_ vcore gpo2 gpo1 sel_vmmc<1:0> pdn_ vmmc type r/w r (1) r (1) 1. these bits are reset (0) after reading r/w r/w r/w r/w bits name value settings default 7 pdn_vaux 0 1 inactive enable ldo vaux 0 6it_warn 0 1 below temperature threshold above temperature threshold 0 5 monitoring_vio_ vmem_vcore 0 1 outputs in the good range outputs lower than expected on vio_vmem or vcore 0 4 gpo2 0 1 output gpo2 hz output gpo2 low 0 3 gpo1 0 1 output gpo1 hz output gpo1 low 0 [2:1] sel_vmmc<1:0> 00 01 10 11 1.8v selection 1.8v selection 2.85v selection 3v selection 00 0 pdn_vmmc 0 1 inactive enable sd/mmc or sdio function. 0 functional description stw4810 28/77 power control register at address 1eh power control register at address 1fh power control register mapping caution: only the latest value written in register at address 1e/1f can be read. table 19. power control register - general information (address = 1eh) register 76543210 bit name reg address 3 bits lsb?s data din/dout 4 bits en type r/w r/w r/w bits name value settings default [7:5] reg address 3 bits see ta bl e 2 1 ?address? column (lsb?s). 0 [4:1] data din/ dout 4 bits see ta bl e 2 1 control register 0 0 en 0 1 read enabled write enabled 0 table 20. power control register - general information (address = 1fh) register 15 14 13 12 11 10 9 8 bit name not used reg address 2 bits msb?s type r/w bits name value settings default [9:8] reg address 2 bits msb?s see ta bl e 2 1 ?address? column (msb?s). 0 table 21. power control register mapping address 1fh address 1eh comment reg address not used 2 bits msb?s 3 bits lsb?s data din/dout 4 bits en 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7654321 0 00h to 04h test purpose 05h to 0ah setting see ta bl e 2 2 to ta bl e 2 7 0bh to 1e test purpose stw4810 functional description 29/77 power control register at address 05h table 22. power control register at address 05h address 1fh address 1eh 15141312111098765 43210 not used 00101 vcore_sel [3:0] en bits name value settings default [4:1] vcore_sel [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 = 1.00v = 1.05v = 1.10v = 1.15v = 1.20v (default) = 1.22v = 1.24v = 1.26v = 1.28v = 1.30v = 1.32v = 1.34v = 1.36v = 1.38v = 1.40v = 1.50v 0100 functional description stw4810 30/77 power control register at address 06h power control register at address 07h table 23. power control register at address 06h address 1fh address 1eh 15141312111098765 4 3 2 1 0 not used 00110 vpll_sel [0] vaux_sel <1:0> usb_ i2c_ctrl en bits name value settings default 4 vpll_sel[1:0] on 06h and 07h address 00 01 10 11 = 1.05v = 1.2v = 1.3v = 1.8v 11 [3:2] vaux_sel[1:0] 00 01 10 11 = 1.5v = 1.8v = 2.5v = 2.8v 00 1 usb_i2c_ctrl 0 1 usb i2c interface controls usb registers main i2c interface controls usb registers 0 table 24. power control register at address 07h address 1fh address 1eh 15141312111098765 4 3 2 1 0 not used 00111en_vpll not used en_ vcore vpll_sel [1] en bits name value settings default 4 en_vpll 0 1 disabled / vpll = off enabled / vpll = on (1) 1. no soft start feature at supply enabled after a disabled/enabled sequence 1 2 en_vcore 0 1 disabled / vcore = off enabled / vcore = on (1) 1 1 vpll_sel[1] - see ta bl e 2 3 - stw4810 functional description 31/77 power control register at address 08h power control register at address 09h table 25. power control register at address 08h address 1fh address 1eh 15141312111098765 43210 not used 01000 en_clk square r en_mo nitorin g en_ vana not used en bits name value settings default 4 en_clock_squarer 0 1 disabled enabled (sine wave signal input) 0 3 en_monitoring 0 1 disabled / monitoring = off enabled / vcore & vio_vmem monitoring = on 1 2 en_vana 0 1 disabled / vana = off enabled / vana = on 1 table 26. power control register at address 09h address 1fh address 1eh 15141312111098765 43210 not used 01001 vaux_ sleep not used not used not used en bits name value settings default 4 vaux_sleep 0 1 when pwren is low: vaux stays in normal mode vaux goes in sleep mode (default) 1 2 not used reserved 1 1 not used reserved 1 functional description stw4810 32/77 power control register at address 0ah twarning register table 27. power control register at address 0ah address 1fh address 1eh 15141312111098765 43210 not used 01010 vaux_ force_ sleep not used vio_ vmem_ force_ sleep vcore_ force_ sleep en bits name value settings default 4 vaux_force_sleep 0 1 0: vaux in normal mode 1: vaux goes in sleep mode (for any pwren level) 0 2 vio_vmem_force_ sleep 0 1 0: vio_vmem in normal mode 1: vio_vmem goes in sleep mode (for any pwren level) 0 1 vcore_force_sleep 0 1 0: vcore stays in normal mode 1: vcore goes in sleep mode (for any pwren level) 0 table 28. twarning register (address = 20h) register 76543210 bit name not used mask_ twarn type -r/w bits name value settings default 0 mask_twarn 0 1 inactive mask twarn interruption (it_twarn bit) through vddok 0 stw4810 functional description 33/77 4.2.6 it generation stw4810 has three interrupt balls: it_wake_up : with only vbat supply, no other supply available, when a usb cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (active low). usbintn : this interrupt ball is dedicated to usb protocol and sent to multimedia processor vddok : this ball has two functions: - when high, it indicates that vio_vmem and vcore output voltages are within the right range and that the device internal temperature is below the maximum allowed temperature. - when low, it indicates that output regulators (vcore or vio_vmem) are not regulated properly or pwren = ?0?, or that the temperature is above the allowed threshold (see thermal shut-down section). the interruption source in the application register (address 11h) needs to be checked. 4.2.7 clock switch ing and control this block generates the clock used by the dc/dc converter (usb charge pump, step-down vio_vmem and step-down vcore). stw4810 is able to sustain the master clock frequencies of 26 mhz, 19.2mhz and 13 mhz. it can also sustain dedicated master_clk signal in the frequency range of 750khz to 1mhz. if the clock is not detected the internal oscillator is automatically selected. note: when present the master clock should remain connected up to sleep mode. figure 9. clock switching between master and internal clock (1) int_osc pon int_osc_ok master_clk_ok pdn_int_osc control_switch step_down_clk third rising edge after switching internal clock external clock transition * phase delay is less than 90 between int and ext clock master_div_clk functional description stw4810 34/77 4.3 power management module stw4810 includes several regulators that supply the multimedia processor and its peripherals. all regulators can work in different modes depending on the processor needs. when the stw4810 is in ?low current mode??, the output current is reduced to save energy via the lower quiescent current. the nominal mode is called high power mode (hpm). the mode is selected by pwren signal according to both multimedia processor and stw4810 state. when pwren = ?0?, sleep mode is selected. hpm is selected as default when pwren = ?1?. each regulator has a dedicated battery power supply. it can be powered down by a signal called pdn_regulator_name as shown in the figure 2: stw4810 block diagram . in this mode, the regulator is switched off and only a leakage current is present (max. 1a). vcore, vaux and vpll output voltages are programmable, through main i2c interface, using the ?regulator?_sel[x:0] bits of the power control registers ( ta bl e 2 2 to ta b l e 2 7 ). in addition, an output current limitation prevents high current delivery in case of output short circuit. all multimedia processor power supplies have the same soft start to prevent leakage in the multimedia processor device during the start-up phase. there is an exception with vaux which can be started independently. 4.3.1 bandgap, bias ing and references figure 10. block diagram of biasing and references of the device bg all internal references vref_18 all internal biasing bias generator voltage reference control stw4810 functional description 35/77 4.3.2 vcore regulator: dc/ dc step- down regulator this regulator drives the core of the multimedia processor. vcore is a dc/dc step-down regulator that generates the regulated power supply with very high efficiency. the 15 voltage levels enable dynamic voltage and frequency scaling suitable for any supply voltage of cmos process, they also follow the processor process roadmap. the regulated output voltage levels are adjustable by the power control registers ( ta b l e 2 2 ), via the main i2c interface (sda, scl). the master clock (13, 19.2 or 26 mhz) is automatically detected, squared and divided to generate the switching clock of the smps. when this clock is not available, regulators run the internal rc oscillator. the dc/dc step-donw regulator has the following main features; programmable output voltage, 15 levels from 1.0 v to 1.5 v (vcore_sel [3:0] bits of power control register - ta b l e 2 2 ) 3 power domains: ? ?normal mode? when multimedia processor is in run mode, 600 ma full load ? ?low current mode? when multimedia processor is in sleep mode, 5 ma current capability. fast switching from low current to normal mode. the regulator is in ?low current mode? when multimedia processor is in sleep mode. pwren signal indicates that the multimedia processor is about to switch to run mode. vddok signal indicates to the multimedia processor that all supplies are in the specified range. note: the definition of sleep mode is given in section 4.2.3: sleep mode . ?power down mode? or ?standby mode? when regulator is switched off, no consumption (en_vcore bit of power control register - ta b l e 2 8 ) soft start circuitry at start up, from power off to normal mode, when pon ball changes from ?0? to ?1?. default setting defined by start-up configuration. 4.3.3 vio_vmem regulator: dc/dc step- down regulator vio_vmem step-down regulator has the same structure than vcore. the vio_vmem regulator supplies the ios of the multimedia processor and its peripherals. this regulator can be used to supply the memories working with the multimedia processor, such as ddr-sdram. a switched mode power supply - voltage down converter is used to generate the 1.8 v regulated power supply with very high efficiency. the master clock (13, 19.2 or 26 mhz) is automatically detected, squared and divided to generate the smps switching clock. when this clock is not available, regulators can run the internal rc oscillator. main features fixed 1.8 v output voltage two power domains: ? ?normal mode? when multimedia processor is in run mode - 600 ma full load ? ?low current mode? when multimedia processor is in sleep mode, 5 ma current capability. functional description stw4810 36/77 fast switching from low current to normal mode. the regulator is in ?low current mode? when multimedia processor is in sleep mode. pwren signal indicates that the multimedia processor is about to switch to run mode. vddok signal indicates to the multimedia processor that all supplies are in the specified range. note: the definition of sleep mode is given in 4.2.3: sleep mode section. soft start circuitry at start up, from power off to normal mode, when pon ball changes from ?0? to ?1?. default setting defined by start-up configuration. 4.3.4 vpll this ldo is dedicated to the multimedia processor pll (1.05 v, 1.2 v, 1.3 v, 1.8 v) power supply with 10 ma max full load (power control registers - ta b l e 2 7 and ta bl e 2 8 ). main features programmable output voltage, (vpll_sel[1:0] bits of power control register - ta b l e 2 7 and ta b l e 2 8 ) two power domains: ? ?normal mode? 10 ma full load ? ?power down mode? or ?standby mode? when regulators are switched off and there is no power consumption (en_vpll bit of power control register - ta b l e 2 8 ) soft start circuitry at start up, from power off to normal mode, when pon ball changes from ?0? to ?1?. default setting defined by start-up configuration. 4.3.5 vana this ldo is dedicated to the multimedia processor analogue function (2.5 v) power supply with 10 ma full load. main features: 2.5 v output voltage, two power domains ? ?normal mode? 10 ma full load ? ?power down mode? or ?standby mode? when regulators are switched off and there is no power consumption (en_vana bit of power control register - ta bl e 2 9 ), default setting defined by start-up configuration. stw4810 functional description 37/77 4.3.6 vaux this ldo is dedicated either to the multimedia processor input/output signals or to the auxiliary devices. power supply values are 1.5 v,1.8 v, 2.5 v, 2.8 v with 150 ma full load and 0.5 ma in sleep mode. in case of 1.5 v on the output, this ldo can be supplied by using vio_vmem dc/dc converter (1.8 v). one pad feed-back is used. main features: programmable output voltage, 4 levels (vaux_sel[1:0] bits of power control register - ta b l e 2 7 ) three power domains: ? ?normal mode? when multimedia processor is in run mode, 150 ma full load ? ?low current mode? when multimedia processor is in sleep mode, 0.5 ma current capability. fast switching from low current to normal mode. note: definition of sleep mode is given in 4.2.3: sleep mode section. ? ?power down mode? or ?standby mode? when regulator is switched off, no power consumption (pdn_vaux bit of sd mmc control register - ta bl e 1 8 ) default setting defined by start-up configuration 4.3.7 power s upply monitoring this block monitors the vcore and vio_vmem output voltage. if vcore or vio_vmem drop below the threshold, the multimedia processor is reset. this feature can be desactivated by setting en_monitoring bit of power control register ( ta b l e 2 9 ) to ?0?. 4.3.8 power supply domains ta b l e 2 9 lists the register bits that control stw4810 supply domains for each supply. note: more details on vmmc supply are given in section 4.5 table 29. power supply domains supply name description supply domains normal sleep power down vcore step-down 15 values vcore_sel[3:0] vcore_sleep vcore_force_sleep en_vcore vio_vmem step-down 1.8 v vio_mem_sleep vio_vmem_force_sleep vpll ldo 4 values vpll_sel[1:0] en_vpll vana ldo 2.5 v en_vana vaux ldo 4 values vaux_sel[1:0] vaux_sleep vaux_force_sleep pdn_vaux vmmc ldo 3 values sel_vmmc[1:0] pdn_vmmc functional description stw4810 38/77 4.3.9 thermal shut-down a thermal sensor is used to monitor the die temperature. as soon as the die temperature exceeds the thermal warning rising threshold 1, vddok ball goes to ?0? and ?it_warn? bit is set to ?1? (sd mmc control register - ta bl e 1 8 ). the ic turns back vddok ball to ?1? and ?it_warn? bit to ?0? when the device temperature drops below the thermal warning falling threshold 1 of the thermal sensor. a second thermal detection level, thermal shutdown rising threshold 2, puts all stw4810 supplies off, the supplies goes back to on state when the temperature reaches the thermal shutdown falling threshold 2. figure 11. thermal threshold temperatures for ?it_warn? bit and vddok ball table 30. thermal threshold values description min typ max unit thermal warning threshold 1 rising threshold 134 140 149 c falling threshold 117 123 131 c thermal shutdown threshold 2 rising threshold 149 155 164 c falling threshold 129 135 143 c ?it_warn? bit vddok ball temperature rising warning threshold 1 rising shutdown threshold 2 all supplies are turn ?off? stw4810 functional description 39/77 4.4 usb otg module this transceiver complies with the usb specification; universal serial bus specification rev 2.0 on the go supplement to the usb specification rev 1.0-a car kit interface specification (see: otg transceiver specification rev0.92) the usb otg transceiver has two modes: usb mode and uart mode. it includes; full and low speed transceiver (12 mbit/s and 1.5 mbit/s data rate) support data line and vbus pulsing session request contains host negotiation protocol (hnp) command and status register charge pump regulator (5 v at 100 ma) to supply vbus line of the usb cable vbus pull-up and pull-down resistors as defined by session request protocol (srp) vbus threshold comparators vusb ldo internal regulator which provides power supply for the bus driver and receiver. id line detector and interrupt generator dedicated i2c serial control interface functional description stw4810 40/77 4.4.1 block diagram figure 12. usb otg transceiver block diagram vusb vbat_usb vusb_ldo vbat_dig vminus_dig out_diff_rx control registers tranceiver vbat_usb id cp cn vbus dp dn charge pump 5v - 100ma oe_tp_int dat_vp seo_vm rcv suspend vp vm id_float id_gnd vbus_vld sess_vld vbus_session_end dp vbus_monitor dp_monitor vbus > 4.4 v 2v < vbus < 4.4 v vbus < 0.8v id detector diff tx diff rx se_dp se_dn d ecoder s ingle rxd rxd speed dat_se0 bdis_acon_en oe_int_en uart_en dp_pullup dn_pullup dp_pulldown dn_pulldown id_gnd_forced vbus_drv vbus_dischrg vbus_chrg dp_hi id_gnd dn_hi bdis_acon gnd ra_bus_in clk ref rpu_dn rpu_dp rpd_dn rpd_dp r_vbus_srp r_vbus_pd vbus_chrg vbus_dischrg dn_pullup dn_pulldown id_gnd dp_pullup dp_pulldown usbvp usbvm usboen usbrcv cr_int interrupt control register vbus_vld sess_vld id_float cr_int usb_intn usbscl usbsda suspend vbus_drv e nded it_wake_up plug detect management sess_vld rid_pu r 4.7 r r scl sda dp < [0.4 to 0.6] v 5.7 r r or 0.85*id 0.15*id 100 ma usb_i2c_ctrl sw_resetn usb_en vbat_dig vbat_usb stw4810 functional description 41/77 vbus monitoring these comparators monitor the vbus voltage. they detect the current status of the vbus line: vbus > 4.4 v means vbus_valid 2 v stw4810 functional description 43/77 the transceiver receives usb data in the following conditions: uart_en = 0 (usb control register 1); oe_int_en = 1 uart mode uart mode is entered by setting the ?uart_en? bit to 1 (usb control register 1 - ta b l e 1 1 ). the transceiver contains two digital logic level translators between the following balls: txd signal: from usbvm to dn rxd signal: from dp to usbvp when not in uart mode the level translators are disabled. table 33. data receiver via usb control register 1 usb mode (dat_se0) suspend inputs outputs dp dn usbvp usbvm usbrcv 1 (dat_se0 mode) 0 0 0 diff rcv 1 1 not used 1 (dat_se0 mode) 0 1 0 1 0 not used 1 (dat_se0 mode) 0 0 1 0 0 not used 1 (dat_se0 mode) 0 1 1 diff rcv 1 0 not used 1 (dat_se0 mode) 1 0 0 0 1 not used 1 (dat_se0 mode) 1 1 0 1 0 not used 1 (dat_se0 mode) 1 0 1 0 0 not used 1 (dat_se0 mode) 1 1 1 1 0 not used 0 (vp_vm mode) 0 0 0 0 0 diff rcv 1 0 (vp_vm mode) 0 1 0 1 0 1 0 (vp_vm mode) 0 0 1 0 1 0 0 (vp_vm mode) 0 1 1 1 1 diff rcv 1 0 (vp_vm mode) 1 0 0 0 0 not used 0 (vp_vm mode) 1 1 0 1 0 not used 0 (vp_vm mode) 1 0 1 0 1 not used 0 (vp_vm mode) 1 1 1 1 1 not used functional description stw4810 44/77 vbus monitoring and control the monitoring is made of three comparators that determine if the vbus voltage is at a valid level for operation: vbus valid: it corresponds to the minimum level on vbus. any voltage on vbus below the threshold is considered to be a fault. during power-up, it is expected that this comparator output is ignored. vbus session valid: this threshold is necessary for session request protocol to detect the vbus pulsing. vbus session end: session is ended. in this usb block, a b-device session end threshold is defined within the range [0.2; 0.8] v. the reason for a low 0.2 v limit is that the leakage current could charge the vbus up to 0.2 v (maximum). when the a-device (default master) is power supplied and does not supply vbus, it presents an input impedance ra_bus_in on vbus of no more than 100 k ? . if the a-device responds to the vbus pulsing method of srp, then the input impedance ra_bus_in may not be lower than 40 k ? . when the a-device supplies power, the rise time ta_vbus_rise on vbus to go from 0 to 4.4 v is less than 100 ms when driving 100 ma and with an external load capacitance of 10 f (in addition to vbus decoupling capacitance). if vbus does not reach this voltage within ta_vbus_rise maximum time, it indicates that the b-device is drawing more current that the a-device is capable of providing and an over-current condition exists. in this case, the a-device turns vbus off and terminates the session. vbus capacitance a dual-role device must have a vbus capacitance cdrd_vbus value comprised between 1 f and 6.5 f (see charge pump specification). the limit on the decoupling capacitance allows a b-device to differentiate between a powered-down dual-role device and a powered- down standard host. the capacitance on a host is higher than 96 f. data line pull-down resistance when an a-device is idle or acting as host, it activates the pull-down resistors rpd on both dp and dn lines. when an a-device is acting as peripheral, it disables rpd on dp, not dn. the a-device can disable both pull-down resistors during the interval of a packet transmission when acting as either host or peripheral. the two bits of usb control register, dn_pulldown and dp_pulldown ( ta bl e 1 2 ) are used to connect/disconnect the pull-down resistors. when the line is not used, the pull-down is activated and the maximum level on this ball should not exceed 0.342 v. data line pull-up resistance full-speed and low-speed devices are differentiated by the position of the pull-up resistor from the peripheral device. a pull-up resistor is connected to dp line for a full-speed device and a pull-up resistor is connected to dn line for a low-speed device. the pull-up resistor value is in the range of 900 ? to 1600 ? when the bus is idle and 1425 ? to 3100 ? when the upstream device is transmitting. stw4810 functional description 45/77 the two bits of usb control register dp_pullup and dn_pullup ( ta b l e 1 2 ) are used to connect/disconnect pull-up resistors. session request protocol (srp) to save power, the otg supplement allows an a-device to leave the vbus turned off when the bus is not being used. if the b-device wants to use the bus when vbus is turned off, then it requires the a-device to supply power on vbus using the session request protocol (srp). initial conditions the b-device does not attempt to start a new session until it has determined if the a-device has detected the end of the previous session. the b-device must ensure that vbus is below vbus_session_end before requesting a new session. additionally, the b-device switches a pull-down resistor (r_vbus_pd) from vbus to ground in order to quicken the discharge process as long as the b-device does not draw more than 8 ma from vbus. r_vbus_pd is activated by bit ?vbus_dischrg? of usb control register 2, ( ta bl e 1 2 ). when the b-device detects that vbus is below the vbus_session_end and that both dp and dn have been low (seo) for at least 2 ms, then any previous session on the a- device is over and a new session can start. data-line pulsing to indicate a request for a new session using the data line pulsing, the b-device turns on the dp pull-up resistor for 5 ms to 10 ms (only at full speed, no dn pulsing). the dp pull-up resistor is connected to vusb (regulator output voltage). timing is controlled by the usb digital control. vbus pulsing to indicate a request for a new session using the vbus pulsing method, the b-device waits for the initial conditions and then drives vbus. vbus is driven for a long enough period for a capacitance on vbus that is smaller than 2x6.5 f to be charged to 2.1 v while a capacitance on vbus higher than 97 f is not charged above 2.0 v. in this usb block, the vbus_session_valid threshold is used to determine if an a-device is drd (dual role device) or a standard host. the b-device vbus pulsing block is designed so that the maximum drawn current does not exceed 8 ma. in this usb block, the pull-up is 600 ? +/- 30%. if a b-device is attached to a standard device, the pull-up must be disconnected after the defined timing to prevent damage of standard hosts not designed to withstand a voltage externally applied to vbus. session request protocol (srp) if the b-device is in correct condition to start a new session, it first performs data line pulsing, followed by vbus pulsing. when vbus next crosses the session valid threshold, the b- device considers a session to be in progress and asserts the dp or dn data line within 100 ms. after srp initialization, the b- device is set up to wait for at least 5 seconds for the a-device to respond before informing the user that the consumption attempt has failed. functional description stw4810 46/77 host negotiation protocol (hnp) at the start of a session, the a-device has the role of host as default. during a session, the host role can be transferred back and forth between the a-device and the b-device any number of times using the host negotiation protocol (hnp). the process for this exchange of host role is described in the ?on the go supplement to the usb 2.0 specification? (rev 1.0). id detector in either active or suspended power mode, the id detector detects the condition of the id line and differentiates between the following three conditions: ? id ball floating: (e.g. with usb b-device connected) ? id ball shorted to ground: (e.g. with usb a-device connected) ? id ball connected to ground through resistor racc_id: (e.g.with an accessory). the transceiver pulls the id ball to vid_hi (vbat) through a resistance of rid_pu when an accessory is plugged in. in this case, the id ball is externally connected to ground via racc_id resistor. two comparators are used to detect the id voltage: vid_gnd and vid_float. the id detector also has a switch that can be used to ground the id ball. this switch is controlled by id_gnd bit of usb control register 2 ( ta bl e 1 2 ); this pull-down is used for cea_karkit purposes. car kit interrupt detector the transceiver is able to detect when the dp line is below the carkit interrupt threshold ?cr_int?, (see usb interrupt register) (refer to otg specifications, rev 0.92, 2.7, p13). charge pump from vbat_usb, the charge pump supplies vbus, ?vbus_drv? bit of usb control register 2 ( ta b l e 1 2 ) is used to enable/disable the charge pump. ldo usb from vbat_usb, a ldo provides vusb supply, ?usb_en? bit of usb_en register ( ta bl e 1 7 ) is used to enable/disable the vusb ldo. stw4810 functional description 47/77 4.4.3 usb enable control stw4810 off in this state, the overall system is able to detect usb connection through it_wake_up ball and with vbus session valid comparator and id detection on. it_wake_up is activated (low level) in either of the two following cases: ? when mini a connector cable is connected and id goes low ? when activity on vbus, i.e. a mini b is connected and is able to communicate. this mode is used to wake-up the modem platform. in this configuration, usbintn ball is not enabled. stw4810 on, usb driver not enabled the usbintn is now enabled. if the usb cable is already connected while stw4810 is starting, the usb driver will be enabled when power management is ready. wake-up usb driver conditions ? a plug-in on a mini a-device and active id detector ? b device is connected and ready to start data transfer, vbus is driven high (session valid high) ? activity on usb registers (00h to 0fh - ta b l e 9 to ta b l e 1 6 ). multimedia processor ready to wake-up and set-up usb phy. ? possibility to force phy high (enable) when writing usb_en = 1 in usb en register ( ta bl e 1 7 ) set condition: one among the following possibilities ? external it_wake_up =0 ? usb_en = 1 by writing to i2c usb interface ? access to any other usb register (00h to 0fh) power down usb driver conditions in order to set the usb driver to power down mode: ? it_wake_up = 1, and only then ? set usb_en bit of usb en register ( ta b l e 1 7 ) to ?0? functional description stw4810 48/77 4.5 sd/mmc/sdio module this block provides the power supply (1.8 v, 2.85 v or 3 v) and signal shifting functions required to connect any of the following peripherals to the multimedia processor: ?sd card ? mmc cards, low and 52 mhz high speed ? sdio cards (except sdio card version 1.0 / vsupply range: [3.1; 3.6] v cards detection is automatically done by the multimedia processor system. following a card detection, the multimedia processor starts the sd/mmc application by writing in the sd mmc control register ( ta b l e 1 8 ) to start ldo vmmc and then starts the protocol initialization. the module includes: ? 1.8 v, 2.85 v or 3 v voltage regulators (150 ma) ? five bidirectional level shifter channels compatible with 1.8 v, 2.85 v or 3 v ? two unidirectional lines for clock: multimedia processor to card and feedback clock to multimedia processor for synchronization. ? four control signals for channel direction figure 13. sd mmc block diagram sd/ mmc/sdio interface 1.8v,2.85v,3v vbat_vmmc vmmc driver level shifter latchclk clkout dataout0 mcclk mcfbclk mccmddir mcdata0dir mcdata31dir mccmd mcdata[3:1] mcdata0 sd, mmc sdio or cards cmdout 5 * rb dataout[3:1] vsdc2 emif rs dz dz rc mcdata2dir 3 * ra 3 * ra 150ma stw4810 electrical and timing characteristics 49/77 5 electrical and timing characteristics otherwise specified parameters are defined for t = 25c. / vbat = 3.6 v 5.1 absolute maximum rating 5.2 package dissipation 5.3 power supply note: stw4810 has different ways to go in sleep mode. the different possibilities for vcore, vio_vmem and vaux to be programmed to sleep mode are given in ta bl e 3 0 and ta b l e 2 7 . in all the following tables: ? ?normal mode? is defined as ?sleep = ?0?? ? ?sleep mode? is defined as ?sleep = ?1?? use ta b l e 2 7 to refer to each vxxx supply (vcore or vio_vmem or vaux). table 34. stw4810 absolute maximum ratings symbol description min. typ. max. units maximum power supply -0.5 7 v ta maximum operating ambient temperature -30 85 c tj maximum junction temperature -30 125 c maximum power dissipation 0.92 w esd performance (1) 1. : hbm mil-std-883 method 3015 2kv table 35. package dissipation symbol description min. typ. max. units tfbga 84 6x6x1.2mm 0.5mm ball pitch rth j-a thermal resistance junction to ambient 70 c/w vfbga84 4.6x4.6x1.0mm 0.4mm ball pitch rth j-a thermal resistance junction to ambient 76 c/w electrical and timing characteristics stw4810 50/77 5.3.1 operating conditions 5.3.2 vref18 table 36. operating conditions (temp range: -30 to +85 c) symbol description test conditions min. typ. max. units v bat power supply 2.7 5.5 v i qsleep quiescent current sleep mode 170 250 a i qstdby off mode 4 a table 37. vref18 symbol description test conditions min. typ. max. units v bat supply voltage 2.7 4.8 v v ref_18 output voltage 1.78 1.8 1.84 v psrr power supply rejection ratio vpp = 0.3 v f 100 khz 60 db noise 100 hz f 100 khz 30 v t s settling time 7.77 9.46 ms stw4810 electrical and timing characteristics 51/77 5.3.3 vcore dc/dc step-down converter table 38. vcore dc/dc step-down converter symbol description test conditions min. typ. max. units vcore regulator in normal mode (sleep = ?0?) / otherwise specified; vcore = 1.2 v v bat input power supply battery voltage 2.7 3.6 4.8 v v ripple output voltage ripple 10 mvpp v out programmable output voltage vcore_sel[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 (default) 0011 0010 0001 0000 -3.7% -4.25% -5% 1.50 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00 +3.7% +4.25% +5% v i out output current 600 ma p eff power efficiency v bat = 3.6 v i out = 200 ma 86 % l ir line regulation v bat : [2.7; 4.8]v 10 mv l dr (1) load regulation i out : [0.1; 600] ma 10 mv i short short circuit current limitation 0.9 1.2 1.4 a i q quiescent current i out = 0 ma 130 250 a i lkg power-down current ?en_vcore? = 0 1 a psrr (1) power supply rejection vpp = 0.3 v [0; 20] khz 40 db l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 7mv l drt transient load regulation i out = [1; 600] ma t r = t f = 100 ns 70 mv electrical and timing characteristics stw4810 52/77 5.3.4 vio_vmem dc/dc step-down converter vcore regulator in sleep mode (sleep= ?1?) v bat input power supply battery voltage 2.7 3.6 4.8 v v ripple vcore output voltage ripple 10 mvpp l ir line regulation v bat : [2.7; 4.8]v 10 mv l dr load regulation i out : [0.1; 5] ma 10 mv i out vcore output current 5ma p eff power efficiency v bat = 3.6 v i out : [0.1; 5] ma 85 % i q quiescent current i out = 0 ma 20 30 a l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 7mv 1. guaranteed by design table 38. vcore dc/dc step-down converter (continued) symbol description test conditions min. typ. max. units vcore regulator in normal mode (sleep = ?0?) / otherwise specified; vcore = 1.2 v table 39. vio_vmem dc/dc step-down converter symbol description test conditions min. typ. max. units vio_vmem regulator in normal mode (sleep = ?0?) v bat input power supply battery voltage 2.7 3.6 4.8 v v out output voltage (1) -3% 1.8 +3% v v ripple output ripple 10 mvpp l ir line regulation v bat : [2.7; 4.8]v 10 mv l dr (2) load regulation i out : [0.1; 600] ma 10 mv i out output current 600 ma p eff power efficiency vbat = 3.6 v, vio = 1.8 v i out = 100 ma 90 % i short short circuit current limitation 0.9 1.2 1.4 a i q quiescent current i out = 0 ma 130 250 a psrr (2) power supply rejection vpp = 0.3 v [0; 20] khz 40 db l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 7 mv stw4810 electrical and timing characteristics 53/77 l drt transient load regulation i out = [1; 600] ma t r = t f = 100 ns 70 mv vio_vmem regulator in sleep mode (sleep=?1?) v bat input power supply battery voltage 2.7 3.6 4.8 v v ripple output ripple 10 mvpp l ir line regulation v bat : [2.7; 4.8]v 10 mv l dr load regulation i out : [0.1; 5] ma 10 mv i out output current 5 ma p eff power efficiency v bat = 3.6 v i out = [0.1; 5] ma 85 % i q quiescent current i out = 0 ma 15 a l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 7 mv 1. including output voltage temperature coefficient, dc line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. guaranteed by design table 39. vio_vmem dc/dc step-down converter (continued) symbol description test conditions min. typ. max. units vio_vmem regulator in normal mode (sleep = ?0?) electrical and timing characteristics stw4810 54/77 5.3.5 ldo regulators vpll table 40. ldo regulators - vpll symbol description test conditions min. typ. max. units vpll regulator in normal mode / otherwise specified, vpll = 1.8 v v bat input power supply battery voltage 2.7 3.6 4.8 v v out output voltage vpll_sel[1:0] 11 (default) 10 01 00 -3% 1.8 1.3 1.2 1.05 +3% v i out output current 3.5 10 ma i short short-circuit limitation 95 130 165 ma i q quiescent current i out = 0 ma 30 40 a i lkg power-down current en_vpll = 0 1 a psrr (1) 1. guaranteed by design power supply rejection vpp = 0.3 v f < 10 khz 10 khz < f <100 khz 55 45 db db l ir line regulation v bat : [2.7; 4.8]v 5 mv l dr load regulation i out : [0.1; 10] ma 10 mv l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 1 mv l drt transient load regulation i out = [0.1; 10] ma t r = t f = 1 s 1 mv en (1) noise density at 1 khz bw = 100 hz 250 nv rms hz ------------ - stw4810 electrical and timing characteristics 55/77 vana vaux table 41. ldo regulators - vana symbol description test conditions min. typ. max. units vana regulator in normal mode v bat input power supply battery voltage 2.7 3.6 4.8 v v out output voltage -5% 2.5 +5% v i out output current 10 ma i short short-circuit limitation 39 51 64 ma i q quiescent current i out = 0 ma 30 a i lkg power-down current en_vana = 0 1 a psrr (1) 1. guaranteed by design power supply rejection vpp = 0.3 v f < 10 khz 45 db l ir line regulation v bat : [2.7; 4.8] v 5 mv l dr load regulation i out : [0.1; 10] ma 5 mv l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 3 mv l drt transient load regulation i out = [0.1; 10] ma t r = t f = 1 s 15 mv table 42. ldo regulators - vaux symbol description test conditions min. typ. max. units vaux regulator in normal mode (pdn_vaux= 1, sleep= ?0?) v bat input power supply v out = 1.5v 1.7 4.8 v v out = 1.8/2.5 v 2.7 3.6 4.8 v v out = 2.8 v 3 3.6 4.8 v out output voltage vaux_sel[1:0] 00 (default) 01 10 11 -3% 1.5 1.8 2.5 2.8 +3% v i out output current 150 ma i short short-circuit limitation 500 700 900 ma i q quiescent current i out = 0 ma 30 a electrical and timing characteristics stw4810 56/77 i lkg power-down current pdn_vaux = 0 1 a psrr (1) power supply rejection v out =1.5 v vpp = 0.3 v f < 10 khz 32 db l ir line regulation v out =1.5 v v bat : [2.7; 4.8]v 5mv l dr (1) load regulation v out =1.5 v i out = [0.1; 150] ma 10 mv l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 2mv l drt transient load regulation i out = [10; 90%] ma t r = t f = 1 s 35 mv t s settling time 100 s vaux regulator in sleep mode (pdn_vaux= 1, sleep=?1?) v bat input power supply v out = 1.5v vio_vmem supply 1.7 4.8 v v out = 1.8/2.5 v 2.7 3.6 4.8 v v out = 2.8 v 3 3.6 4.8 v out output voltage vaux_sel[1:0] 00 (default) 01 10 11 -3% 1.5 1.8 2.5 2.8 +3% v i out output current 500 a i q quiescent current i out = 0 ma 15 a psrr (1) power supply rejection v out =1.5 v vpp = 0.3 v f < 10 khz 38 db l ir line regulation v out =1.5 v v bat : [2.7; 4.8]v 5mv l dr load regulation v out =1.5 v i out = [10; 90%] a 10 mv l irt transient line regulation ? v bat = 300 mv t r = t f = 10 s 2mv l drt transient load regulation i out = [10; 90%] a t r = t f = 1 s 35 mv 1. guaranteed by design table 42. ldo regulators - vaux (continued) symbol description test conditions min. typ. max. units vaux regulator in normal mode (pdn_vaux= 1, sleep= ?0?) stw4810 electrical and timing characteristics 57/77 5.3.6 power s upply monitoring this block monitors the vcore and vio_vmem output voltage. if vcore or vio_vmem drops below the threshold, the multimedia processor is reset. 5.4 digital specifications 5.4.1 cmos input/output static characteristics: i2c interface table 43. power supply monitoring symbol description test conditions min. typ. max. units threshold t hcore (1) 1. guaranteed by design threshold vcore -3% vcore- 150 +3% mv t hvio (1) threshold vio_vmem -3% 1.65 +3% v comparators v bat supply voltage 2.7 3.6 4.8 v t res response time 100 ns h yfall hysteresis (input voltage falling) 26 mv h yris hysteresis (input voltage rising) +4 mv table 44. cmos input/output static characteristics: i2c interface symbol description test conditions min. typ. max. units i2c interface (1) 1. vio is for vio_vmem v il low level input voltage 0.3*v io v v ih high level input voltage 0.7*v io v i il low level input current -1.0 1.0 a i ih high level input current -1.0 1.0 a v ol low level output voltage iol = 3ma (with open drain or open collector) 0.2*v io v v oh high level output voltage iol = 3ma (with open drain or open collector) 0.8*v io v electrical and timing characteristics stw4810 58/77 5.4.2 cmos input/output dynamic characteristics: i2c interface table 45. cmos input/output dynamic characteristics: i2c interface symbol description min. typ. max. units i2c interface ( figure 8 ) fscl clock frequency 400 khz thigh clock pulse width high 600 ns tlow clock pulse width low 1300 ns tr sda, scl, usbsda, usbscl rise time 20+0.1*cb (1) 1. cb = total capacitance of one bus line in pf 300 ns tf sda, scl, usbsda, usbscl fall time 20+0.1*cb 300 ns thd_sta start condition hold time 600 ns tsu_sta start condition set up time 600 ns thd_dat data input hold time 0 ns tsu_dat data input set up time 250 ns tsu_sto stop condition set up time 600 ns tbuf bus free time 1300 ns cb capacitive load for each bus line 400 pf stw4810 electrical and timing characteristics 59/77 5.4.3 cmos input/output static characteristics: vio level usb and control i/os table 46. vio level: usb and control i/os symbol description test conditions min. typ. max. units sw_resetn, vddok, porn, pwren, tcxo_e n, request_mc, clk32k, clk32k_in, usboen, usbvp, usbvm, usbrcv, usbintn, master_clk v il (1) 1. vio for vio_vmem low level input voltage 0.3*vio v v ih high level input voltage 0.7*vio v i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a c in input capacitance 10 pf v ol low level output voltage iol = tbd 0.2*vio v v oh high level output voltage iol = tbd 0.8*vio v t of output fall time capacitance 10pf tbd ns t or output rise time capacitance 10pf tbd ns c i/o driving capability 100 pf electrical and timing characteristics stw4810 60/77 mmc interface table 47. vio level: mmc interface symbol description test conditions min. typ. max. units mmc interface: mcclk, mcfbclk, m ccmddir, mccmd, mcdata2dir, mcdat2, mcdata0dir, mcdat0, mcdat31dir, mcdat3, mcdat1 v il (1) 1. vio for vio_vmem low level input voltage 0.3*vio v v ih high level input voltage 0.7*vio v i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a c in input capacitance 10 pf v ol low level output voltage iol = tbd 0.2*vio v v oh high level output voltage iol = tbd 0.8*vio v c i/o driving capability at 52 mhz 30 pf stw4810 electrical and timing characteristics 61/77 5.4.4 cmos input/output stat ic characteristics: vbat level table 48. cmos input/output static characteristics: vbat level symbol description test conditions min. typ. max. units it_wake_up, pon, gpo1, gpo2 v il low level input voltage pon 0.3*vbat v v ih high level input voltage pon 0.7*vbat v i il low level input current pon -1.0 1.5 a i ih high level input current pon -1.0 1.5 a c in input capacitance 10 pf v ol low level output voltage it_wake_up, gpo1, gpo2 iol = tbd 0.2*vbat v v oh high level output voltage it_wake_up, gpo1, gpo2 iol = tbd 0.8*vbat v t of output fall time capacitance 10pf tbd ns t or output rise time capacitance 10pf tbd ns c i/o driving capability 100 pf electrical and timing characteristics stw4810 62/77 5.4.5 cmos input/output static characteristics: vmmc level table 49. cmos input/output static characteristics vmmc level symbol description test conditions min. typ. max. units dataout0, dataout1, dataout2, dataout3, cmdout, latchclk, clkout v il low level input voltage 0.3*vmm c v ih high level input voltage 0.7*vmm c i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a c in input capacitance 10 pf v ol low level output voltage i ol = tbd 0.2*vmm c v oh high level output voltage i ol = tbd 0.8*vmm c c i/o driving capability 40 pf stw4810 electrical and timing characteristics 63/77 5.5 usb otg transceiver table 50. usb otg transceiver symbol description test conditions min. typ. max. units uart mode t r rise time c load = [50;100] pf [10; 90] % of v oh -v ol 100 ns t f fall time c load = [50;100] pf 10......90% of v oh -v ol 100 ns t plh drive propagation delay low => high c load = [50;100] pf 50% of |v oh -v ol | 100 ns t phl drive propagation delay high => low c load = [50;100] pf 50% of |v oh -v ol | 100 ns usb full speed mode (dp & dn signals) t r rise time usbvp & usbvm : - trise & tfall < 1 ns - skew < 0.66 ns 420ns t f fall time 4 20 ns d rfm differential rise an fall time matching 90 111 % os cv output signal crossover voltage 1.3 2 v p del propagation delay 18 ns usb low speed mode (dp & dn signals) t r rise time 75 300 ns t f fall time 75 300 ns d rfm differential rise an fall time matching 80 125 % os cv output signal crossover voltage 1.3 2 v vbus comparators v bat input power supply battery voltage 3.1 3.6 4.8 v t rr rising reacting time 1.7 s t fr fall reacting time 2.1 s electrical and timing characteristics stw4810 64/77 threshold vbus monitoring v bval vbus valid 4.4 4.5 4.6 v v bses vbus session valid 1.8 2 v vbus r a_bus_ in 40 100 k ? t a_vbus_ rise v bus = [0; 4.4] v i load = 100ma external cap 10f 100 ms data line pull-down resistance r pd_dpdn 14 19 25 k ? data line pull-up resistance r pu_dp bus idle bus driven 900 1425 1200 2300 1600 3100 ? r pu_dn bus idle bus driven 900 1425 1200 2300 1600 3100 ? pull-down on vbus r vbus_pd 650 925 1200 ? pull-up on vbus r vbus_srp 420 600 780 ? id v id_gnd id_gnd comparator threshold 2.7 v < v bat < 4.8 v 0.15*v b at v v id_hi (v bat ) battery level 2.7 3.6 4.8 v v id_float id_float comparator threshold 0.85*v b at v r pu_id 70 100 130 k ? r pd_id 10 k ? carkit threshold detection c r_int carkit interrupt threshold 0.4 0.6 v table 50. usb otg transceiver (continued) symbol description test conditions min. typ. max. units uart mode stw4810 electrical and timing characteristics 65/77 transceiver v oh_txd_ dat txd output high on dn i source = 500 a 2.4 3.6 v v ol_txd_ dat txd output low on dn i sink = 2ma 0.4 v v ih_rxd _dat rxd input high on dp 2v v il _ rxd_ dat rxd input low on dp 0.8 v charge pump v bat input power supply battery voltage vusb+0.1 3.6 4.8 v v bus output voltage current load up to 100 ma 4.75 5 5.25 v t s settling time [0;4.8] v) ext. load: 100 ma + external cap = 10f 1.2 ms iq quiescent current no load 2.7 ma vripple amplitude output ripple on vbus current load 8 ma current load 100ma 25 40 mv mv i out output current 100 ma eff efficiency v bat = 3.0v i out =100ma vbat= 3.6v. i out = 8 ma. 85 60 % % vusb regulator v bat (1) input voltage battery voltage: v bat min = v out + 0.1v vusb+0.1 3.6 5.5 v v out output voltage v bat min= v out + 0.1v 3.0 3.1 3.2 v i short short circuit current limitation 320 ma i q quiescent current no load 70 a psrr (2) power supply rejection v bat = v out +0.2v f < 20 khz 45 db n vout output noise voltage v bat = v out +0.2v 10hz stw4810 electrical and timing characteristics 67/77 t s settling time off->on i out = 0 ma 100 s t d discharge time on>off i out = 0 ma 1 ms bus line specifications ra (2) pull-up resistor to prevent bus floating 1.5 m ? rb pull-down resistor to prevent bus floating 1.5 m ? f dt clock frequency data transfert mode with cl = 30pf 52 mhz f id clock frequency identification mode with cl = 30pf 400 khz t phc propagation time from host to card figure 14 7ns t pch propagation time from card to host figure 14 7ns t shc clock /data skew time from host to card figure 14 reference is clkout +/- 0.5 ns t sch clock /data skew time from card to host figure 14 reference is mmclk +/- 0.5 ns t r rise time 3 ns t f fall time 3 ns c1 line between multimedia processor & stw4810 bus line capacitance f < 52 mhz 20 (3) pf c2 line between stw4810 & mmc card bus line capacitance f < 52 mhz 20 + 20 (4) pf 1. guaranteed by design 2. mmc interface pull up resistors are in emif06-hcm01f2 device (7 k ? for cmd; 75 k ? for data wires) 3. 20 pf for equivalent board parasitic capacitance. 4. 20 pf for emif06 protection + 20 pf for board paras itic capacitance. table 51. sd/mmc card interface (continued) symbol description test conditions min. typ. max. units vmmc regulator specifications (pdn_vmmc = 1) electrical and timing characteristics stw4810 68/77 figure 14. propagation and clock/data skew times mcclk mccmd mcdata[3:0] mcfbclk t 50% 2 ns 2 ns 10% 90% 10% 90% t 50% t phc clkout cmdout dataout[3:0] latchclk t phc mcclk mccmd mcdata[3:0] mcfbclk t 50% 2 ns 2 ns 10% 90% 10% 90% t 50% t pch clkout cmdout dataout[3:0] latchclk t pch mcdata[3:0] 2 ns 10% 90% t shc mcclk 50% clkout dataout[3:0] mcdata[3:0] 2 ns 10% 90% t sch mcclk 50% clkout dataout[3:0] stw4810 application information 69/77 6 application information 6.1 components list table 52. components list name typical value comments function c1 22f in the complete system application, the sum of the capacitors connected on each stw4810 ball must never be less than 30% of the value indicated in the typical value column of this table. this includes all capacitor parameters: ? production dispersion ? dc bias voltage applied ? temperature range of the complete system application ?aging vio_vmem output filter c4 vcore output filter c2 10f vbat_viovmem decoupling c3 vbat_ana decoupling c5 vbat_vcore decoupling c6 1f vpll output filter c7 vana output filter c8 vref output filter c10 vusb output filter c13 vaux output filter c9 470nf flying capacitor for charge pump c11 4.7f vbus output filter (tank charge pump capacitor) c12 2.2f vsd_mmc output filter c13, c14, c15, c16, c17 1 f vbattery input voltage decoupling capacitors l1 4.7h see ta bl e 5 3 for recommended coils coil viovmem dc/dc l2 coil vcore dc/dc table 53. recommended coils supplier part number dcr ( ? )irms (1) (a) 1. irms: 30% decrease of initial value l x l x h (mm * mm * mm) tdk vlf3010at-4r7mr70 0.28 0.7 2.8 * 2.6 * 1.0 vlf3012at-4r7mr74 0.16 0.74 2.8 * 2.6 * 1.2 vlf4012at-4r7m1r1 0.14 1.1 3.7 * 3.5 * 1.2 coilcraft do1605t-472mx 0.15 1.1 5.5 * 4.2 * 1.8 do3314-472ml 0.32 1.1 3.3 * 3.3 * 1.4 me3320-472mx 0.19 1.1 3.2 * 2.5 * 2.0 application information stw4810 70/77 table 54. other st components name order code function emif02 emif02usb05 usb esd/emi protection emif06 emif06-hmc01f2 mmc interface esd/emi protection stw4810 application information 71/77 6.2 application schematics figure 15. stw4810 application schematics vlx_viovmem usbvp usboen usbrcv usbvm mccmddir mccmd mcdat0dir vusb scl sda pon mcdat0 mcclk vref latchclk datout[3:1] mcdat31dir mcfbclk cmdout mcdat[3,1] multimedia processor vcore porn clk32k pwren vddok usb 3 vminus_viovmem vbat_viovmem viovmem_fb vbat_ana vminus_ana vbat_vcore vlx_vcore vpll vana cp cn vbus dp dn id esd emi filter vmmc sd mmc sdio clkout modem & system clock 3 clk32kin master_clk sw_resetn it_wake_up l1 c1 c2 c3 l2 c5 c6 c7 c8 c10 c11 c12 r1 r1 vbat_mmc vbat_usb vminus_usb vbat_vpll_vana vminus_dig vbat_dig d3 b9 dataout0 vaux c9 vbat_vaux c13 vminus_vcore c4 usbintn request_mc tcxo_en emi filter usbscl usbsda gpo1 gpo2 emif02 emif06-hmc01f2 mcdat2dir mcdat2 stw4810 card c13 (*) c14 (*) c15 (*) c16 (*) c17 (*) (*) the usefulness of these capacitors depend of pcb layout package mechanical data stw4810 72/77 7 package mechanical data 7.1 tfbga 84 balls see figure 16: tfbga 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . table 55. tfbga 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions (1) 1. these measurements conform to jedec standards drawing dimensions (mm) min. typ. max. a 1.16 a1 0.20 0.25 0.30 a2 0.82 b 0.250.300.35 d 5.906.006.10 d1 4.50 e 5.906.006.10 e1 4.50 e 0.450.500.55 f 0.650.750.85 ddd 0.08 stw4810 package mechanical data 73/77 figure 16. tfbga 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing note: the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. package mechanical data stw4810 74/77 7.2 vfbga 84 balls see figure 17: vfbga 84 balls 4.6x4.6x1.0 mm ball pitch drawing . table 56. vfbga 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch (1) 1. these measurements conform to jedec standards drawing dimensions (mm) min. typ. max. a 0.864 a1 0.15 0.19 0.23 a2 0.615 a3 0.18 a4 0.435 b 0.210.250.29 d 4.554.604.65 d1 3.60 e 4.554.604.65 e1 3.60 e0.40 f0.50 ddd 0.08 eee 0.13 fff 0.04 stw4810 package mechanical data 75/77 figure 17. vfbga 84 balls 4.6x4.6x1.0 mm ball pitch drawing note: the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. revision history stw4810 76/77 8 revision history table 57. document revision history date revision changes 24-jan-06 1 initial release. 7-feb-06 2 modified document title. reviewed list of applications on cover page. replaced ape with multimedia processor. replaced fuse with analogue function. renamed vfuse as vana. modified figure 6 - control interface - i2c format 9-feb-06 3 correction of figure 13: sd mmc block diagram . correction of figure 15: stw4810 application schematics . 10-mar-2006 4 correction in section 4.2.3: sleep mode on page 18 - removed formula and some text about sleep mode. table 26: power control register at address 09h on page 31 - replaced bit 2 and 1 with ?not used? and ?reserved?. stw4810 77/77 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual 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